Modern superscalar processors often have a large number of pipelines which read and write to a large number of physical registers stored in one or more shared register files. However, it is not practical to allow each of the pipelines to access a single register file without making the register file multi-cycle access (e.g. the register file can't be accessed in a single cycle) which reduces performance of the processor.
Accordingly, many superscalar processors implement register file caching where the pipelines write and read to one or more register file caches. However, where the processor has a large number of pipelines the register file caches typically still have a large number of ports. Although these ports present less of a problem than on the main register file (as the register file cache is smaller) the ports require a large number of wires to be routed between all of the pipelines and the register file caches.
The embodiments described below are not limited to implementations which solve any or all of the disadvantages of known processors.